The invention lies in the semiconductor technology field. More specifically, the invention relates to an MRAM semiconductor memory configuration wherein a plurality of planes with MRAM main cell arrays in the form of a crosspoint array or transistor array together with redundant MRAM cell arrays comprising redundant MRAM memory cells are provided on the same chip.
In magnetoresistive memories (MRAMs), the memory effect resides in the magnetically variable electrical resistance of the memory cell. FIG. 1 shows an individual MRAM memory cell having, at the crossover between two conductors, a word line WL and a bit line BL, which are generally arranged orthogonally with respect to one another. Stacked one above the other are a hard-magnetic layer ML (fixed), a tunnel oxide TL and a soft-magnetic layer ML (free), which together form an MTJ memory cell (MTJ=Magnetic Tunnel Junction). Information is stored by rotating the magnetization direction of the soft-magnetic layer ML (free) relative to that of the hard-magnetic layer ML (fixed). The requisite magnetic fields are generated by currents IWL, IBL respectively through the word line WL and the bit line BL, which are superposed at the crossover point. If the magnetization direction of both magnetic layers is identical, the multilayer system comprising ML (fixed), TL and ML (free) has a low resistance Rc. If the magnetization direction is not identical, a high resistance Rc is produced. This change in resistance is utilized for information storage in digital memory applications.
Extremely high storage density can be achieved by a plurality of metalization systems with intervening planes comprising MTJs being stacked one above the other.
FIGS. 2A and 2B show a magnetoresistive semiconductor memory configuration in a crosspoint array structure which makes it possible to produce a high-density semiconductor memory configuration. An MRAM crosspoint array of this type achieves an extremely high packing density by stacking the individual memory arrays one above the other.
FIG. 3 shows an MRAM semiconductor memory configuration which differs from the crosspoint array structure of FIGS. 2A and 2B. This MRAM transistor array is distinguished by a selection transistor T which is assigned to each MRAM memory cell and which can be used to select individual MRAM memory cells for writing and reading. The gates of mutually assigned selection transistors T, for example of a row, are interconnected by a selection line AL, while the drain paths of the selection transistors T of a column are interconnected by a programming line PL.
If memories having a high storage capacity are realized, then the integration of redundant memory elements on the chip is of significant importance in order to ensure a sufficiently high yield during chip fabrication. In this case, when the memory is tested, defective memory cells are replaced by the additionally available redundant memory cells.
Commonly assigned U.S. Pat. No. 6,351,408 (German patent application DE 197 44 095 A) describes an MRAM memory cell arrangement wherein the memory elements are arranged one above the other in at least two layers. In this case, the bit lines are provided separately in each case for memory elements S1 and S2 and the word line is provided jointly for both memory elements. This arrangement of MRAM memory cells stacked one above the other has the effect that the area requirement per memory element decreases and the packing density can be increased. At no point, however, does this document describe an MRAM semiconductor memory configuration wherein a plurality of planes with MRAM main cell arrays in the form of a crosspoint array or transistor array together with redundant MRAM cell arrays comprising redundant MRAM memory cells are provided on the same chip. This is because, as mentioned above, an MRAM main cell array in each case comprises memory cells and the associated bit, word and, if appropriate, selection lines, which are thus provided separately for each MRAM main cell array.
U.S. Pat. No. 6,154,413 describes a memory architecture, also for an MRAM semiconductor memory wherein a plurality of so-called xe2x80x9cmemory tilesxe2x80x9d are arranged in an integrated circuit chip. The memory tiles could also be considered as memory subarrays. These memory tiles are integrated next to one another in the same plane. In order to increase the reliability, this document proposes that each memory subarray is assigned its own redundant memory rows and/or columns and a corresponding redundancy control circuit arrangement. In this case, the redundant memory cell columns and rows are each fixedly assigned to a main memory cell array of a memory tile.
U.S. Pat. No. 5,381,370 proposes that a main memory cell array is fixedly assigned a redundant cell array in such a way that it is possible to address the main memory cell array and the redundant memory cell array with the same column address.
It is accordingly an object of the invention to provide an MRAM semiconductor memory configuration with redundant cell fields, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for advantageous structural concepts for redundancy to be provided in MRAM semiconductor memory configurations.
With the foregoing and other objects in view there is provided, in accordance with the invention, an MRAM semiconductor memory configuration, comprising:
a memory matrix of a plurality of MRAM main cell arrays arranged in a crosspoint array or a transistor array and a plurality of redundant MRAM cell arrays formed with redundant MRAM memory cells, the plurality of MRAM main cell arrays together with the plurality of redundant MRAM cell arrays being disposed in a plurality of planes commonly integrated in a given chip; and
wherein the redundant MRAM cell arrays are distributed over individual the planes of the memory matrix such that defective memory cells in one plane can be replaced with redundant memory cells from other planes.
In the case of the crosspoint array structure of an MRAM semiconductor memory configuration, in accordance with one aspect of the invention, the redundant cell arrays can be distributed over the individual planes of the memory matrix. In other words, a defective MRAM memory cell need not necessarily be replaced by redundant memory cells in the same plane, but rather can be replaced by means of redundant cell arrays from other planes of the memory matrix. This affords the advantage of smaller cell arrays per plane in order to achieve a comparable yield. This leads to a saving of chip area.
With the above and other objects in view there is also provided, in accordance with the invention, an MRAM semiconductor memory configuration having a memory matrix of a plurality of MRAM main cell arrays arranged in a crosspoint array or a transistor array and a plurality of redundant MRAM cell arrays formed with redundant MRAM memory cells, the plurality of MRAM main cell arrays together with the plurality of redundant MRAM cell arrays being disposed in a plurality of planes commonly integrated in a given chip, and an improvement according to which one of the planes of the MRAM semiconductor memory configuration is used in its entirety for redundant cell arrays.
That is, in accordance with a second aspect of the invention, the MRAM semiconductor memory configuration arranged in a crosspoint array structure can have a complete redundant plane wherein redundant cell arrays are provided.
In order to be able to replace the defective memory cells, the addresses of the defective word and bit lines must be stored in a nonvolatile manner. This can be done by means of electrical fuses. In the case of a crosspoint array structure of an MRAM semiconductor memory configuration, the area below the cell array can be utilized for circuits for storing the addresses of the defective lines, i.e. word lines and bit lines.
In an advantageous refinement, the addresses of the defective word and bit lines can be stored in special MTJ-E fuses. These E fuses are, in principle, normal MRAM memory cells and can be brought to electrical breakdown with an increased voltage. MTJ-E fuses of this type can be realized by means of a dedicated MTJ layer above the memory array.
Redundant bit lines BL are more important than redundant word lines in crosspoint arrays since, owing to the complex read method, parasitic currents through defective memory cells on the bit lines have a significantly more harmful effect on the sense amplifier than on the driver circuit on the word line. Therefore, the invention proposes providing a larger number of redundant bit lines than word lines.
It is advantageous that, in the case of an MRAM memory configuration according to the invention in a crosspoint array structure, for the case of defective cells, which then have excessively low resistances, the word lines and/or bit lines are connected up in a high-impedance manner in order to suppress disturbing influences. In the case of an MRAM semiconductor memory configuration which is arranged in a transistor array structure in accordance with FIG. 3, it is possible, moreover, to deactivate defective memory cells by switching off the gates of the selection transistors on the corresponding word line WL by means of the selection line which connects the gates of the selection transistors T. In the case of short circuits between bit lines BL and programming lines on account of cell defects, it is possible to employ the principle of connecting up in a high-impedance manner, already mentioned for the case of a crosspoint array structure.
It is also the case with an MRAM semiconductor memory configuration organized in a transistor array structure in accordance with FIG. 3 that the addresses of the defective word and bit lines can be stored in MTJE fuses. These MTJE fuses can also be arranged directly above the MRAM transistor array.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a mram semiconductor memory configuration with redundant cell arrays, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.